[SOLVED] Getting all 0's in setup view and N/A in reg2reg column after optDesign -preCTS in cadence Innovus

[pskol95]

Hello Everyone,
I have inserted IO pads in the design.
I have "create_clock" command in the sdc (from synopsys dc)
After running "optDesign -preCTS" I am getting as shown in picture.
Where am I doing mistake ?

 

[ThisIsNotSam]

probably everywhere since your design is empty...

you can do report_timing even before you do placement. if you see nothing in there, your setup is wrong. revise mmmc, sdc, rtl, etc...

 

[pskol95]

probably everywhere since your design is empty...

you can do report_timing even before you do placement. if you see nothing in there, your setup is wrong. revise mmmc, sdc, rtl, etc...

Without IO pad, I am able to report_design before placement, but with IO pad using same setup as, I'm getting -
"No contrainted timing paths found. Design may not be constrained or library is missing timings information"

Surely, library is not missing any information, so what can I do ?
I am using the same sdc, which has create_clock command and set_input_delay, set_output_delay etc command automatically generated during synthesis using design compiler.

Thanks !

 

[pskol95]

Without IO pad, I am able to report_design before placement, but with IO pad using same setup as, I'm getting -
"No contrainted timing paths found. Design may not be constrained or library is missing timings information"

Surely, library is not missing any information, so what can I do ?
I am using the same sdc, which has create_clock command and set_input_delay, set_output_delay etc command automatically generated during synthesis using design compiler.

Thanks !

sorry .. report_timing** before placement