gatelevel simulation error

[siva_7517]

ncelab output port was not connected

In gatelevel simulation there is a statement :

ncelab: *W,CUVWSP (./fft14_mapped.v,812|27): 1 output port was not connected:
ncelab: (/tools/Silterra_fe/aci/sc-x/verilog/silterra18.v,9586): QN
EDFFX1 in_buf_im_reg_3__8_ ( .D(in_im[8]), .E(n485), .CK(clk), .Q(

Why are this problem occurs?

 

[bulx]

Possible that the FF inferred by synthesis is one having a QN output for some reason, but the circuit is not making use of it, but using the Q output only.

-b

 

[aji_vlsi]

Possible that the FF inferred by synthesis is one having a QN output for some reason, but the circuit is not making use of it, but using the Q output only.

-b

Just to add what is said, NC supports "-nowarn WARN_NUMBER" to disable that - if you want to. I would recommend you understand the reason why it comes, then use this option if you need to

Ajeetha, CVC
www.noveldv.com
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5 h**p://www.systemverilog.us/
* SystemVerilog Assertions Handbook
* Using PSL/Sugar

 

[siva_7517]

Hi,

I have notice that all the unconnected out QN is coming from case statement that i have used in verilog. Is this because of my case function as a latch?

Siva

 

[incisive]

Hi

In Netlist optimazation some unconnected nets are removed out and when that
netlist is used for simulation it gives some unconnected port massege.

 

[gong.kidd]

That's warning ,not Error. The module has one more port which is not be connected

 

[wangkl]

Yes, only a warning. And u could ignore that.
For a standard filp-flop cell, there're alway Q and QN. u will not always use both of them. It's normal one of them keep NC.
Any way, pay more attention to *E in your simulation logfile, not *W.