Gate level v/s Timing Simulation

[carrot]

Hi,

What is the differnce between Gate level Simulation & Timing Simulation? What are the Steps to be followed during Timing Simulation.

 

[rsrinivas]

when synthesizing u give constraints like clk uncertainity,load,setup time etc.
these values will not be embedded in the netlist wat u have obtained.
if u simulate this netlist it will be your Gate level Simulation
u can write out the timing file from ur synthesis tool which includes the delay values(in min typ max).if u include this file(sdf - standard delay format) and simulate ur netlist that will be ur timing simulation ,back annotation.

 

[carrot]

Please provide some good links for the topic if u know.

 

[research235]

hello Carrot,

Any material related to ASIC design flow has detailed explanation about this , as an example u can look at Advacned asic design flow by Himanshu Batnagar. The book though deals with only Synopsys tool but still helps in better understanding ..

suresh

 

[satyakumar]

Hi,
The below is ebook which describes in detail about timing in digital circuits, and design based on optimised delay. Hope this gives a detail description how timing is part of digital design.

 

[zengbo]

Perfect!!!
Thanks very much!
I need it.

 

[megastar007]

hi

i dont have enough points to download. what should i do?

 

[xstal]

You keep posting relevent topics and replies. for each replies you get some points.