oAwad
Full Member level 2
Hello all,
I'm simulating a gate level netlist generated from Synopsys Design Compiler. During simulation, I get warnings that some of DFFs in my netlist are missing QN while other DFFs are missing Q
It's normal for Design compiler to produce DFF with either floating Q or QN depending on the need. But this generates a conflict between the DFF definition in my gate level netlist and the attached verilog library (that has all gates function definitions)
for example:
DFF in netlist -> DFF (D,clk,Q) or DFF (D,clk,QN)
DFF in library -> DFF (D,clk,Q,QN)
In the simulation window, I get all outputs to be xxxxxx (red color). So how to solve this in Design Compiler ?
- - - Updated - - -
I'm sorry the problem is with the initial value of DFFs so please discard the above. I have a reset signal in the design but how to connect it to all DFFs ?
- - - Updated - - -
My library already contains some DFF without set/reset while other types have. So how to force Design Compiler to use DFF with set/reset ?
I'm simulating a gate level netlist generated from Synopsys Design Compiler. During simulation, I get warnings that some of DFFs in my netlist are missing QN while other DFFs are missing Q
It's normal for Design compiler to produce DFF with either floating Q or QN depending on the need. But this generates a conflict between the DFF definition in my gate level netlist and the attached verilog library (that has all gates function definitions)
for example:
DFF in netlist -> DFF (D,clk,Q) or DFF (D,clk,QN)
DFF in library -> DFF (D,clk,Q,QN)
In the simulation window, I get all outputs to be xxxxxx (red color). So how to solve this in Design Compiler ?
- - - Updated - - -
I'm sorry the problem is with the initial value of DFFs so please discard the above. I have a reset signal in the design but how to connect it to all DFFs ?
- - - Updated - - -
My library already contains some DFF without set/reset while other types have. So how to force Design Compiler to use DFF with set/reset ?
Last edited: