Gate level simulation

[oAwad]

Hello all,

I'm simulating a gate level netlist generated from Synopsys Design Compiler. During simulation, I get warnings that some of DFFs in my netlist are missing QN while other DFFs are missing Q

It's normal for Design compiler to produce DFF with either floating Q or QN depending on the need. But this generates a conflict between the DFF definition in my gate level netlist and the attached verilog library (that has all gates function definitions)

for example:
DFF in netlist -> DFF (D,clk,Q) or DFF (D,clk,QN)
DFF in library -> DFF (D,clk,Q,QN)

In the simulation window, I get all outputs to be xxxxxx (red color). So how to solve this in Design Compiler ?

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I'm sorry the problem is with the initial value of DFFs so please discard the above. I have a reset signal in the design but how to connect it to all DFFs ?

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My library already contains some DFF without set/reset while other types have. So how to force Design Compiler to use DFF with set/reset ?

 

[ThisIsNotSam]

if the code you are trying to synthesize has reset logic, the correct S/R flip-flop will be instantiated. That's all that is needed. The netlist will connect all the resets automatically for you.