gate level simulation- sdf file how to read clk & reset

[vlsi_maniac]

hi
i was trying to do gate level simulation using quartus and modelsim.
the dut is a counter and it works at 411 MHz.
now if i write the test bench am i supposed to generate the clock in testbench not more than 411MHz.
and i have seen in sdo file the below para

(CELL
(CELLTYPE "stratix_lcell_register")
(INSTANCE count\[0\]\~reg0.lereg)
(DELAY
(ABSOLUTE
(PORT aclr (4809:4809:4809) (4809:4809:4809))
(PORT clk (2479:2479:2479) (2479:2479:2479))
(IOPATH (posedge clk) regout (156:156:156) (156:156:156))
(IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
)
)


what does clk 2479 refers to.

i generated the clock and if the clock is less than 2479 ps(half period) then i am not getting waveforms or the dut is not working.
if reset is less than 4809 ps then dut is not resetting

what does the above indicate.

testbench

module tb_counter ();

reg core_clk;
reg reset_n;
wire [7:0] count;

initial
begin
core_clk <= 1'b1;
forever #2479 core_clk <= ~ core_clk;
end

initial
begin
reset_n <= 1'b0;
repeat(2) @(posedge core_clk);
reset_n <= 1'b1;
end

counter_test counter_u1(
core_clk,
reset_n,
count);

endmodule

please i need this urgently.thanks

 

[devas]

Re: gate level simulation- sdf file how to read clk & re

Hi,

Here the link to the SDF standard:

**broken link removed**

Devas

 

[kujigaya]

if the delay (as specified in the SDF) is greater than the clock period, then the signal changes will not propagate through the cells/nets

you can try to simulate using a lower clock frequency