warriorwithin
Newbie level 4
I want to implement a FSK reciever on an FPGA for 4 channels in (600-2k) hz range. The FPGA has a maximum gate count of about 300k.
Would the area be enough to implement this.
Are there any rules of thumb regarding an FSK reciever and gate count?
Would the area be enough to implement this.
Are there any rules of thumb regarding an FSK reciever and gate count?