Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Gain values in sub 45nm CMOS circuits

Status
Not open for further replies.

rock_on

Newbie level 1
Newbie level 1
Joined
Apr 17, 2009
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,286
what are the gain values I can target for sub 45 nm CMOS processes. For example I would like to design an unity gain buffer in 32 nm tech, I need it to have high gain for the input and output node to track each other pretty well. So how much high on gain can i go in this technology.(Normally in such low dimentions you donot get much high gain).
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top