From VHDL/Verilog to layout

[pichuang]

verilog to layout in mentor graphics

Hi everyone,

I am wondering if it is possible to write a vhdl/verilog code and uses it to generate the schematic and layout so that I can combine it with my own full custom design?

For instance, say I am working on a adder. In order to test the adder, I need to layout not only the adder, but the testing circuitries such as the decoder, PLL, etc as well. My question is, is it possible to implement these circuitries in vhdl/verilog code, and then I can use these codes to generate the schematic and layout?

I am new to this field and I hope I explain my quesiton clear enough. Any hint or guideline are highly appreciated.

Thank you,

Pierce

 

[jbeniston]

vhdl 레이아웃

Yes - you can generate a schematic from VHDL/Verilog code, by synthesizing the code, or by writing purely structural code.

 

[ljxpjpjljx]

for the DUT , you can synthesis! for the test bench , you should write code which can be synthesis , so you can do it as well!

 

[FvM]

Integrated ECAD tools as Altium Designer or Mentor Expedition would be able to perform all requested steps with one tool. Most developers however are using separate tools for logic design/implementation and schematics/layout. One reason is that programmable logic vendor tools as Altera Quartus allow a more intuitive operation and additional features not available with integrated tools.

 

[Clunixchit]

Yes, you can.

Have a look at the cheapest way via Fedora Electronic Lab.
**broken link removed**

 

[khamitkar.ravikant]

it is possible to generate that but you required particular software for that as like MENTOR GRAPHICS tools and also Xilinx ISE for verilog or VHDL code . and you can have it.

 

[pichuang]

Hi everyone,

First of all thanks for the replies. I was told by another graduate student that one way to complete this task is to first write up the verilog code (ex modelsim) then convert it to the gate level design with synopsys design vision. After this I believe a schematic/layout can be generated with another cadence software. I guess I will learn more after the lecture tomorrow.

Again thanks alot for the tips and helps, I will post another reply if I learn anything new.

Pierce