pichuang
Newbie level 6
verilog to layout in mentor graphics
Hi everyone,
I am wondering if it is possible to write a vhdl/verilog code and uses it to generate the schematic and layout so that I can combine it with my own full custom design?
For instance, say I am working on a adder. In order to test the adder, I need to layout not only the adder, but the testing circuitries such as the decoder, PLL, etc as well. My question is, is it possible to implement these circuitries in vhdl/verilog code, and then I can use these codes to generate the schematic and layout?
I am new to this field and I hope I explain my quesiton clear enough. Any hint or guideline are highly appreciated.
Thank you,
Pierce
Hi everyone,
I am wondering if it is possible to write a vhdl/verilog code and uses it to generate the schematic and layout so that I can combine it with my own full custom design?
For instance, say I am working on a adder. In order to test the adder, I need to layout not only the adder, but the testing circuitries such as the decoder, PLL, etc as well. My question is, is it possible to implement these circuitries in vhdl/verilog code, and then I can use these codes to generate the schematic and layout?
I am new to this field and I hope I explain my quesiton clear enough. Any hint or guideline are highly appreciated.
Thank you,
Pierce