FPGA LUT delay for a simple function

[hithesh123]

What is the delay for a simple function implemented in LUT.
Let's say the function is Y=A, where A is the input and Y is the output.
Will there be any prop delay?

 

[FvM]

In a first order, the propagation delay of a true LUT is independent of the implement logic combination.

 

[hithesh123]

In a first order, the propagation delay of a true LUT is independent of the implement logic combination.

what do you mean? The LUT delay is constant?

 

[Toneski_IP]

what do you mean? The LUT delay is constant?

Yes - the LUT delay will be constant and defined in the datasheet for your particular logic device.

If you imagine your logic being implemented within a small RAM, then you can visualise that as long as your logic function is in a single LUT, the propagation delay will always be constant (it would be very wierd for a memory block to have different delays depending on what location you are accessing)