shaiko
Advanced Member level 5
We always make sure that on power-up our FSM is at a known state.
-------------------------
process (clk , rst )
if external_global_reset = '1' then
fsm state <= idle ;
elsif....
-------------------------
"global_reset" is a signal with a dedicated input pin to the FPGA.
But, what if we compile our design without connecting "global_reset" to an input pin at the pin assignment stage ?
Will the internal POR circuitry act the same way as "external_global_reset" and make sure that the FSM loads at an idle state ?
In other words , does the synthesis tool "automatically rewrites" our code and "behind the scenes" it's actually :
if external_global_reset = '1' or POR then
fsm state <= idle ;
?
-------------------------
process (clk , rst )
if external_global_reset = '1' then
fsm state <= idle ;
elsif....
-------------------------
"global_reset" is a signal with a dedicated input pin to the FPGA.
But, what if we compile our design without connecting "global_reset" to an input pin at the pin assignment stage ?
Will the internal POR circuitry act the same way as "external_global_reset" and make sure that the FSM loads at an idle state ?
In other words , does the synthesis tool "automatically rewrites" our code and "behind the scenes" it's actually :
if external_global_reset = '1' or POR then
fsm state <= idle ;
?