shaiko
Advanced Member level 5
Below, is a code for an event detecor inplemented on an FPGA.
The design has an input vector called: "events"
and a steady state value for that vector - called "default_events_vector".
If "events" and "default_events_vector" aren't equal, it means that an event has accured.
This immidiatly changes the state of the asynchronous FSM and switches on an external DSP.
What do you think of the design ?
Any noticeable issues?
The design has an input vector called: "events"
and a steady state value for that vector - called "default_events_vector".
If "events" and "default_events_vector" aren't equal, it means that an event has accured.
This immidiatly changes the state of the asynchronous FSM and switches on an external DSP.
What do you think of the design ?
Any noticeable issues?
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity event_detector is
generic ( event_vector_width : positive := 26 ) ;
port
(
rst ,
dsp_off : in std_logic ;
events : in unsigned ( event_vector_width - 1 downto 0 ) ;
dsp_on : buffer std_logic
) ;
end entity;
architecture synthesizable_event_detector of event_detector is
type fsm_states is
(
fsm_idle_state_0 ,
fsm_on_state_1
) ;
constant default_events_vector : unsigned ( event_vector_width - 1 downto 0 ) := "11100111110001111111111111" ;
signal fsm_state : fsm_states ;
signal event_flag : std_logic ;
begin
event_detecion: process
(
events ,
event_flag
) is
begin
for i in 0 to event_vector_width - 1 loop
if events ( i ) /= default_events_vector ( i ) then
event_flag <= '1' ;
else
event_flag <= '0' ;
end if ;
end loop ;
end process event_detecion ;
asynchronous_fsm : process
(
dsp_on ,
rst ,
fsm_state ,
event_flag ,
dsp_off
) is
begin
if rst = '0' then
dsp_on <= '0' ;
fsm_state <= fsm_idle_state_0 ;
else
case fsm_state is
when fsm_idle_state_0 =>
if event_flag = '1' then
fsm_state <= fsm_on_state_1 ;
dsp_on <= '1' ;
end if ;
when fsm_on_state_1 =>
if dsp_off = '1' then
dsp_on <= '0' ;
fsm_state <= fsm_idle_state_0 ;
end if ;
end case ;
end if ;
end process asynchronous_fsm ;
end architecture synthesizable_event_detector ;