FPGA early I/O pin planning.

[sameerr11]

Hello friend ,

I am working on Cyclon 3 FPGA, EP4C487.I use this FPGA to implement Glue logic.Right now i am not implemeting my software to FPGA, but only designing my PCB. To design schematic of pcb i need to coneect 19 address line and 15 data line (from BF537 DSP) to FPGA.But as it is myfirst project.I little bit confuse how can i assigen FPGA pin to this data and address pin.So please guide me or give me some link from where i can get some idea.

 

[farhada]

HI,
I don't know if this is still useful for you, but with FPGAs generally you can use any pin you want. If the signals are high speed or need to be of a certain standard, then you try to put the signals in the same bank, this way it will be easy to handle them.

Other than that, every thing is pretty straight forward.

Cheers,
/Farhad