archillios
Full Member level 1
hi all,
I am using formality in equivalence checking,it's about gate-to-gate checking.
My ref design is a netlist in which sequential cells are usual DFF,while the implementation design netlist consist sequential cells all made of 2-level latch.
Matching is OK,but in verification phase,almost all sequential compare points failed.
When I debug the failure pattern ,I found that it seems the tools is trying to verify between DFF/Q (ref)and level one latch of 2-Level DFF (imp).
how can I get through this ?
thanks.
I am using formality in equivalence checking,it's about gate-to-gate checking.
My ref design is a netlist in which sequential cells are usual DFF,while the implementation design netlist consist sequential cells all made of 2-level latch.
Matching is OK,but in verification phase,almost all sequential compare points failed.
When I debug the failure pattern ,I found that it seems the tools is trying to verify between DFF/Q (ref)and level one latch of 2-Level DFF (imp).
how can I get through this ?
thanks.