Varun124
Junior Member level 3
Hi ,
In my design due to some reason capture clock is blocked to a flop and faults on the combo logic are undetected .How are we going to tackle this situation during actual silicon test and w.r.t to timing simulation whether the combo logic is valid path to generate SDF ? . If yes how is it valid path , since we are not able to capture the data.
Thanks,
Varun
In my design due to some reason capture clock is blocked to a flop and faults on the combo logic are undetected .How are we going to tackle this situation during actual silicon test and w.r.t to timing simulation whether the combo logic is valid path to generate SDF ? . If yes how is it valid path , since we are not able to capture the data.
Thanks,
Varun