For DFT perspective ,what happens when there are no capture clock

[Varun124]

Hi ,

In my design due to some reason capture clock is blocked to a flop and faults on the combo logic are undetected .How are we going to tackle this situation during actual silicon test and w.r.t to timing simulation whether the combo logic is valid path to generate SDF ? . If yes how is it valid path , since we are not able to capture the data.

Thanks,
Varun

 

[ThisIsNotSam]

Hi ,

In my design due to some reason capture clock is blocked to a flop and faults on the combo logic are undetected .How are we going to tackle this situation during actual silicon test and w.r.t to timing simulation whether the combo logic is valid path to generate SDF ? . If yes how is it valid path , since we are not able to capture the data.

Thanks,
Varun

Is your design academic in nature? Most designs don't have this characteristic, outputs are flopped and for very good reasons.

 

[Tieny]

Hi ,

In my design due to some reason capture clock is blocked to a flop and faults on the combo logic are undetected .How are we going to tackle this situation during actual silicon test and w.r.t to timing simulation whether the combo logic is valid path to generate SDF ? . If yes how is it valid path , since we are not able to capture the data.

Thanks,
Varun

First , I will cause the error when you are doing insertion (C1 violation) and stop your flow !
Second , if your flop cannot capture clock , how can it operate in functional mode ?

 

[Varun124]

Tieny, suppose in my design there are 3 clocks and how are we decided which clock to select as scan clock. And in some post I read (not sure) that only one clock will be active at capture. Why it so.

 

[Tieny]

Tieny, suppose in my design there are 3 clocks and how are we decided which clock to select as scan clock. And in some post I read (not sure) that only one clock will be active at capture. Why it so.

1. If your design is HATPG you can check OCC ( On-chip Clock Control ) for more info. DFT will create 1 scan_clock for this purpose.
2. If your design is not HATPG, it meant you have 3 clock domains , and all 3 of them will be scan_clock . For your statement " 1 clock will be active at capture" I tink it can be " 1 lock domain active " because the timing between 2 clock domain ( please check cross-path)