jimito13
Advanced Member level 1
Hello everybody.I have a very general question...
I am designing a broadband operational amplifier.My first stage consists of the classical folded cascode topology as depicted below.The design kit i use is IBM's cmos9flp (90nm low power).
After lots of simulations and hand calculations i cannot achieve gain better than 30-31dB...Are those values reasonable,i mean is the maximun i can achieve for this combination of topology-design kit or i can go better??
And my question could be more general..How somebody can approximately estimate,before exhaustive simulations and/or hand calculations,that the maximun value for a given specification is " X " under a specific combination of circuit topology and design kit process?
And my second question : Where should i connect the body (B) terminal of the pmos transistors of the input differential pair?At the source (S) of the transistors or at Vdd??
I would appreciate any helpful answer.Thanks in advance.
I am designing a broadband operational amplifier.My first stage consists of the classical folded cascode topology as depicted below.The design kit i use is IBM's cmos9flp (90nm low power).
After lots of simulations and hand calculations i cannot achieve gain better than 30-31dB...Are those values reasonable,i mean is the maximun i can achieve for this combination of topology-design kit or i can go better??
And my question could be more general..How somebody can approximately estimate,before exhaustive simulations and/or hand calculations,that the maximun value for a given specification is " X " under a specific combination of circuit topology and design kit process?
And my second question : Where should i connect the body (B) terminal of the pmos transistors of the input differential pair?At the source (S) of the transistors or at Vdd??
I would appreciate any helpful answer.Thanks in advance.