Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Depending on supply, VT and output position it may
be impractical to get saturation-region operation.
Just because books and professors say it's a Good
Thing doesn't mean it's practical. Sometimes you
have to make up your gain elsewhere or use low-VT
devices to claw back headroom, etc. (at some risk
that their process control puts you on the wrong side
of bias setpoint, and they end up not-gate-controlled
if you try to dial down Vgs to achieve textbook OP).
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
