Flip Flop output and timing with PRESET and CLEAR

[piyush.oct]

what will happen if the PRESET and CLEAR signal of a flip -flop are simultaneously active. how this condition will affect timing of flip flop?

 

[vipinlal]

I think it depends on how you design the flip flop, but generally CLEAR has priority over PRESET.

 

[aVi3467]

Depending on the kind of flipflop and how you have implemented it will decide the operation of PRESET+CLEAR.
Various outcomes include, metastability, PRESET being given priority, vice-versa.

A good example to analyze this situation with will be with passgate flip flop representation, Master and Slave added with the PRESET and CLEAR signals. Then check the results with the NAND gate FF.