Flip flop cell,vhdl netlist simulation, post-synthesis

[draser]

Hello,

i am doing a post-synthesis vhdl netlist simulation and here is the problem i observe:

I observe that the flip flop that change from 1 to 0 change faster than the flip flops that change from 0 to 1.The first ones change i.e. at 200 ps after clock edge and the second ones at 300 ps after clock edge.

Is there any way to make these 2 transition times equal?

Thank you.

 

[ads-ee]

It's probably not a "problem" only you perceive it as a problem. Pretty much any logic cell will have a difference in the delay for outputting a transition of 1->0 and 0->1. Unless the cell is specifically designed to have a balanced and matched delay between the two, you get whatever you get.

If you want to complain about 100 ps difference, then you should have seen the old TTL logic families, they had huge differences between high-low and low-high transitions. Back then it was pretty normal to see 1 ns or more differences.

 

[andre_luis]

Is there any way to make these 2 transition times equal?

Post synthesis simulation just present electric behaviour in function of the physical specifications of the cells. There is no way to you interfere on its properties.

 

[draser]

Well i understand this,but here is my problem:

i have a cell that has inputs A and B that are connected with FlipFlop1 and FlipFlop2 respectively. When these inputs do not change the same time i observe an output glitch.

The only reason that they do not change the same time is if FF1 goes from 1 to 0 and FF2 goes from 0 to 1(and vice versa).

 

[andre_luis]

You are not using proper techniques to synchronize signals at a single clock domain.
Take a search on race conditions and how to avoid that.

 

[ads-ee]

If you are attempting to generate a combinational output based on the two FFs, and use that directly as a control signal then you're not designing your circuit in the most robust fashion, any signal where glitches matter should be generated directly from the output of a FF to avoid the race condition problem andre mentions (the race condition occurs prior to the setup time of FF).

 

[ThisIsNotSam]

Well i understand this,but here is my problem:

i have a cell that has inputs A and B that are connected with FlipFlop1 and FlipFlop2 respectively. When these inputs do not change the same time i observe an output glitch.

The only reason that they do not change the same time is if FF1 goes from 1 to 0 and FF2 goes from 0 to 1(and vice versa).

I really have not a clue what you are trying to achieve here. combinational cells react to input changes, it's how they work. why would you expect these signal to arrive at the same time and why does it matter?

 

[draser]

I really have not a clue what you are trying to achieve here. combinational cells react to input changes, it's how they work. why would you expect these signal to arrive at the same time and why does it matter?

I would like to not get a glitch at the output of my combinational cell,because this cell output is connected with the output of my main design.

In fact i do not know if it does matter.This circuit is an interconnect and the output is going to be connected with a memory,my problem is i do not know when this memory will capture the signal.I dont want it to be captured when the glitch/signal change occurs.

Is it a problem that should be fixed?For example if the clock cycle is 20 ns then the output of my interconnect will be ready i.e. 1 ns after the clock cycle.If the memory captures the signal after 1 ns after the clock cycle,then everything is fine.But what about if it tries to capture it within less 1 ns?

That's why i think if i make these 2 signals come at the same time then i will avoid this glitch,right?As i understand if i cannot make it then the only solution is to add a flip flop between the combinational output and the output of my design!

 

[ads-ee]

Isn't rule number 1 of ASIC design: Register all outputs of your module.

Violating thus rule usually gets everyone pissed at you.

You could always make everyone even more pissed off by using a jk flop to do this without glitches.

 

[draser]

It's my first ASIC design so i did not know this rule!Well i can do it,but i would not like to add more area/power consumption!

However,i think i do not have a choise here !

 

[ThisIsNotSam]

Isn't rule number 1 of ASIC design: Register all outputs of your module.

Violating thus rule usually gets everyone pissed at you.

You could always make everyone even more pissed off by using a jk flop to do this without glitches.

This ^.

If you want to have a combinational output in your module it requires some extra work. For 99% of the cases it is not worth it.

 

[ads-ee]

For 99% of the cases it is not worth it.

Yeah that 1% is usually due to some stupidly designed protocol with a absolute turn around time that has to occur in the same clock cycle. Of course this protocol is used because it worked in the past (at 33 MHz) and the justification for using it instead of a modern bus protocol is ASICs are faster now so we can run it at 250 MHz.