Ironlord
Member level 3
Hello mates!
I am trying to do a LVDS communication for testing purposes before the real project. The aim is to communicate via LVDS with a high-speed ADC @ 800mbps. On my test, I have used a Terasic DE10-Nano development board (which does not accomplish with the desired voltages) and it went quite well. The FPGA inside is a Cyclone V 5CSEBA6U23I7. I created a project and added the following IP Cores: LVDS_TX, LVDS_RX and PLL. Everything went right!
The basic project for testing was a loopback communication. The VHDL code sends 8-bits signals for 4 LVDS Channels through LVDS_TX. Through the switches and LEDs on the board, I can decide which channel to see represented. The LVDS_RX receives the signal, and with the PLL I create a 100Mhz clock, which I also send and receive using the GPIO pins.
As the project became bigger, I acquired another FPGA, an Enclustra Mercury PE1 with the Mercury SA2 module. It has a Cyclone V 5CSTFD6D5F31I7 FPGA. I replicated the same project, but I had some troubles.
-1st. I had to create a Platform Designer System to get a clock signal from the HPS. I decided to use a 50Mhz signal.
-2nd. The project i replicated didn't work, so after looking for the error on Google and reading the Intel/Altera forums, people suggested to use the ALTCLKCTRL megafunction. I obtained the same problem.
-3rd. Finally, i decided to create another 100MHz clock from the system, using the HPS. So I exported another clock signal and deleted the PLL module, because it wasn't needed no more. I still getting the same messages on the fitter.
I don't know what I am doing wrong or what should I do. On the Enclustra I am using the FMC connector to get the signals, and I bought the expansion board Terasic F2G to convert those hard to reach pins into GPIO pins. I only have access to the banks 4A and 8A. I write on the following paragraph the error messages:
Could you help me with this issue? Thanks a lot in advance.
I am trying to do a LVDS communication for testing purposes before the real project. The aim is to communicate via LVDS with a high-speed ADC @ 800mbps. On my test, I have used a Terasic DE10-Nano development board (which does not accomplish with the desired voltages) and it went quite well. The FPGA inside is a Cyclone V 5CSEBA6U23I7. I created a project and added the following IP Cores: LVDS_TX, LVDS_RX and PLL. Everything went right!
The basic project for testing was a loopback communication. The VHDL code sends 8-bits signals for 4 LVDS Channels through LVDS_TX. Through the switches and LEDs on the board, I can decide which channel to see represented. The LVDS_RX receives the signal, and with the PLL I create a 100Mhz clock, which I also send and receive using the GPIO pins.
As the project became bigger, I acquired another FPGA, an Enclustra Mercury PE1 with the Mercury SA2 module. It has a Cyclone V 5CSTFD6D5F31I7 FPGA. I replicated the same project, but I had some troubles.
-1st. I had to create a Platform Designer System to get a clock signal from the HPS. I decided to use a 50Mhz signal.
-2nd. The project i replicated didn't work, so after looking for the error on Google and reading the Intel/Altera forums, people suggested to use the ALTCLKCTRL megafunction. I obtained the same problem.
-3rd. Finally, i decided to create another 100MHz clock from the system, using the HPS. So I exported another clock signal and deleted the PLL module, because it wasn't needed no more. I still getting the same messages on the fitter.
I don't know what I am doing wrong or what should I do. On the Enclustra I am using the FMC connector to get the signals, and I bought the expansion board Terasic F2G to convert those hard to reach pins into GPIO pins. I only have access to the banks 4A and 8A. I write on the following paragraph the error messages:
Code:
Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 fractional PLL(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (175020): The Fitter cannot place logic fractional PLL in region (0, 73) to (0, 81), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The fractional PLL name(s): LVDS_RX:LVDS_RX_inst|altlvds_rx:ALTLVDS_RX_component|LVDS_RX_lvds_rx:auto_generated|pll_sclk~FRACTIONAL_PLL
Info (175013): The PLL output counter is constrained to the region (0, 73) to (0, 81) due to related logic
Info (175015): The I/O pad inFrame[0] is constrained to the location PIN_H14 due to: User Location Constraints (PIN_H14)
Info (14709): The constrained I/O pad is driven by a PLL LVDS output, which is driven by a PLL output counter, which is contained within this fractional PLL
Error (11238): The following 1 fractional PLL locations are already occupied, and the Fitter cannot merge the previously placed nodes with these instances. The nodes may have incompatible inputs or parameters.
Error (11239): Location FRACTIONALPLL_X0_Y74_N0 is already occupied by LVDS_TX:LVDS_TX_inst|altlvds_tx:ALTLVDS_TX_component|LVDS_TX_lvds_tx:auto_generated|pll_fclk~FRACTIONAL_PLL.
Info (175013): The PLL output counter is constrained to the region (0, 73) to (0, 81) due to related logic
Info (175015): The I/O pad outFrame[0] is constrained to the location PIN_A6 due to: User Location Constraints (PIN_A6)
Info (14709): The constrained I/O pad is driven by a PLL LVDS output, which is driven by a PLL output counter, which is contained within this fractional PLL
Error (12289): An error occurred while applying the periphery constraints. Review the offending constraints and rerun the Fitter.
Could you help me with this issue? Thanks a lot in advance.