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I get the following warnings during clock tree synthesis:
#WARNING (NREX-28) The height of the first routing layer M1 is 0.000000. It should be larger than 0.000000
#WARNING (NREX-29) The metal thickness of routing layer M1 is 0.000000. It should be larger than 0.0. Add this to the technology information for better accuracy.
#WARNING (NREX-30) Please also check the height and metal thickness values for the routing layers heigher than routing layer M1
#WARNING (NREX-4) No Extended Cap Table was imported. Not enough process information was provided either and default Extended Cap Table database will be used.
I have checked my LEF file and the widths of the metal layers have been defined. After CTS, Encounter returns over 1000 violations (related to shorts). There are no violations encountered after placement.
What could be the problem?
#WARNING (NREX-28) The height of the first routing layer M1 is 0.000000. It should be larger than 0.000000
#WARNING (NREX-29) The metal thickness of routing layer M1 is 0.000000. It should be larger than 0.0. Add this to the technology information for better accuracy.
#WARNING (NREX-30) Please also check the height and metal thickness values for the routing layers heigher than routing layer M1
#WARNING (NREX-4) No Extended Cap Table was imported. Not enough process information was provided either and default Extended Cap Table database will be used.
I have checked my LEF file and the widths of the metal layers have been defined. After CTS, Encounter returns over 1000 violations (related to shorts). There are no violations encountered after placement.
What could be the problem?
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