anandhavel
Newbie level 2
Hi,
If I specify a net in a verilog module, is it possible to find the primary inputs and path to the specified nets in either PrimeTime or DesignCompiler?
Thanks,
Anand
If I specify a net in a verilog module, is it possible to find the primary inputs and path to the specified nets in either PrimeTime or DesignCompiler?
Thanks,
Anand