fatal error in ram implementation

[qwerty_asdf]

This is my ram implementation:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY ram2 IS
	GENERIC
	(
		ADDRESS_WIDTH	: integer := 14;
		DATA_WIDTH	: integer := 24
	);
	PORT
	(
		clock			: IN  std_logic;
		data			: IN  std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);
		write_address			: IN  integer range 0 to 100;--std_logic_vector(ADDRESS_WIDTH - 1 DOWNTO 0);
		read_address			: IN  integer;--std_logic_vector(ADDRESS_WIDTH - 1 DOWNTO 0);
		we			: IN  std_logic;
		q			: OUT std_logic_vector(DATA_WIDTH - 1 DOWNTO 0)
	);
END ram2;

ARCHITECTURE rtl2 OF ram2 IS
	TYPE RAM IS ARRAY(0 TO 2 ** ADDRESS_WIDTH - 1) OF std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);

	SIGNAL ram_block : RAM;
BEGIN
	PROCESS (clock)
	BEGIN
		IF (clock'event AND clock = '1') THEN
			IF (we = '1') THEN
			    --ram_block(to_integer(unsigned(write_address))) <= data;
				ram_block(write_address) <= data;
				q <= ram_block(read_address);
			END IF;
			--q <= ram_block(to_integer(unsigned(read_address)));
			--q <= ram_block(read_address);
		END IF;
	END PROCESS;
END rtl2;

If the address_widht is 3, and data_size is 8 everything works perfect.

With the number above I am getting this error:

Fatal: (vsim-3738) (vopt-1154) No index value can belong to null index range 0 to -1.
#    Time: 1920850 ns  Iteration: 1  Process: /tb_landmark_1/uut/write_res/#MERGED#line__27,27,27 File: C:/modeltech_6.5/examples/ram2.vhd
# Fatal error in Block write_res at C:/modeltech_6.5/examples/ram2.vhd line 32

and in my simulation window ram_block is NULL array.

Can anyone help me on that?

 

[TrickyDicky]

I get the feeling you set address width to 0 when you instantiated the ram.
also with a write address 0 to 100 you vannot cover all addresses when addr width is greater than 6