Fast Lookahead carry logic for Xilinx device

[ChaXi]

Hello to everybody.
I'm trying to understand the fast lookahead carry chain contained in the SliceM/L of most xilinx device...
Can someone explain wich operation is done to CYINIT and CIN (the result goes into the first MUXCY)?
I'm referring to page 34 of the Spartan6 Configurable Logic Block (UG384).

Can someone know some reference to understand how this block can be used?

Thx to everyone

Chaxi

 

[mrflibble]

CIN is used when the carry input comes from the carry output from the previous slice. So CIN is generally used when this CARRY4 block is further along the carry chain.

CYINIT is used for the other cases. So when you want a static 0 or 1 as the carry input, or a variable carry input that comes from any place other than the previous slice. For that case the AX input to the CLB is used.

For a simple adder, CYINIT will be used for the LSB CARRY4 element, and CIN for all the following CARRY4 elements.

Hope that clarifies things.

---------- Post added at 20:51 ---------- Previous post was at 20:18 ----------

Edit: Forgot to mention ... a good way to see what's happening is to make a simple 16-bit adder, and then view the post place & route results in FPGA Editor.

 

[ChaXi]

Perfect! I was not making a 16 bit adder, but some logic of mine in which it's very important to connect CO3 of previous stage with CIN of the next and having for the first stage a carry = 0 (like in the adder).
I didn't arrive to post place and route phase because when i saw the RTL schematics it appeared that the CIN where not connected (but there is no messagge of this in the synthesis message) and i thought the problem was some my mistake in the inputs CIN, CYINIT for the Carry4. This is how i connected.

First stage (LSB)

if n = 0 generate
			begin
			CARRY4_inst : CARRY4
					port map (	
						CO 		=> carry_hit_out((4*n)+3 downto 4*n),    -- 4-bit carry out
						O 		=> open,          					        -- 4-bit carry chain XOR data out
						CI 		=> '0',       					              -- 1-bit carry cascade input
						CYINIT 	=> '0',                                                       -- 1-bit carry initialization
						DI 		=> carry_hit_chain((4*n)+3 downto 4*n),    -- 4-bit carry-MUX data in
						S 			=> inverter((4*n)+3 downto 4*n)   -- 4-bit carry-MUX select input
					);

other stages

U3: if (n > 0) generate
			begin
			CARRY4_inst : CARRY4
					port map (
						CO 		=> carry_hit_out((4*n)+3 downto 4*n),         
						O 		=> open,                                                      -- 4-bit carry chain XOR data out
						CI 		=> carry_hit_out((4*(n-1))+3),                        -- 1-bit carry cascade input
						CYINIT 	=> '0',                                                          -- 1-bit carry initialization
						DI 		=> carry_hit_chain((4*n)+3 downto 4*n),          -- 4-bit carry-MUX data in
						S 			=> inverter((4*n)+3 downto 4*n)             -- 4-bit carry-MUX select input
					);

CIN is used when the carry input comes from the carry output from the previous slice.

CYINIT is used for the other cases.

For a simple adder, CYINIT will be used for the LSB CARRY4 element, and CIN for all the following CARRY4 elements.

According to this I should put: first stage CIN => 'Z'
other stage CYINIT => 'Z'

Am I correct?

Thanks

CHAXI

 

[mrflibble]

According to this I should put: first stage CIN => 'Z'
other stage CYINIT => 'Z'

Am I correct?

That would indeed seem correct. I seem to recall that in my code I simply did not do an assignment to the wires as opposed to assigning a 'Z'. But that should have the same result as your code with assigning a Z.

What I do know for sure is that your original code above that assigns to BOTH CI and CYINIT will be a no-go, since the mapper cannot map this to any valid device configuration. Just take a look at the MUX on page 34 from the pdf, you can either use CI, or CYINIT, but not both.

---------- Post added at 15:49 ---------- Previous post was at 15:46 ----------

Oh yeah .. Can I ask what this is for? I always have an interest in creative use of carry chains.

 

[ChaXi]

ok I understand the mux but still have sintax problem:

I simply did not do an assignment to the wires

Can you explain more in detail what do you mean by that?
Because I get some errors in both cases... when using 'Z' I get this error while running map:

The CARRY4 "FirstHit[15].U3.CARRY_SEL" has a connected CI and
CYINIT pin.Please connect only one of these pins.

and when not assigning no value ( CI/CYINIT => ,) i get error in synthax...

Can you please explain me in detail how not connect one of them? Sorry but i'm learning now about vhdl.

P.S.
It's a sort of project for my school: the Lut inside the slice have some little logic and I need to communicate some information beetween them... the mux inside the carry are used as simply OR of DI and CO.. it's just to learn how to use fpga resource...

 

[mrflibble]

I'm sorry, I misremembered the 'Z' / unconnected stuff from something else to do with the CARRY4.

Couple of code snippets from working code:

wire [(NUM_ELEMENTS-1):0] cyinit;
wire   [(NUM_ELEMENTS):0] cin;     // one extra element for overflow...


if (USE_CYINIT==1) begin
    assign cyinit[(NUM_ELEMENTS-1):0] = { {(NUM_ELEMENTS-1) {1'b0}}, pulsetrain_in}; // 1st CYINIT from slice LUT
    assign cin[0]                     = 1'b0;
end else begin
    assign cyinit[(NUM_ELEMENTS-1):0] = {(NUM_ELEMENTS) {1'b0}}; 
    assign cin[0]                     = pulsetrain_in; // 1st CIN from previous CARRY4
end

genvar i;
generate
for (i=0; i<(NUM_ELEMENTS); i=i+1) begin:FOURTAPS

CARRY4 CARRY4_packed (
    .CO     (cin[i+1]),
    .O      (xor_out[i]),
    .CI     (cin[i]),
    .CYINIT (cyinit[i]),
    .DI     (4'b0001),
    .S      (4'b1111)
    );
end
endgenerate

This was spread over 2 modules along with other code, so I had to edit it a little. Hope this makes things clear.

Here "pulsetrain_in" is the input into the carry chain. And with USE_CYINIT you can select if it came from a LUT or from the previous carry out.

So in summary, yes you do need to assign both CIN and CYINIT. And only one of those can be a non-zero value. Which re-reading your first post is kinda strange, since it seems you already did that. I only somewhat read VHDL though, so any sneaky details will go right over my head.

Maybe something is going wrong during the generate? You could try to do just 2 CARRY4 elements and wire those explicily, just to see how you should wire them properly.

 

[ChaXi]

Ok I tried connecting only two of them, all works properly either in behavioral either post route simulation: to get the correct functionality you must put to '0' the input you don't use as you said and as I did on the first time. When using just two carry4 I get all the the connection in the rtl schematic, while using all the carry I need (41) some connections disappear... I found in other forum (I don't know if i can post a link to other forum btw it's the official one) that this is because newer version of ISE have some problem with that and this is confirmed by experience... so I think that mine can be one of this case...thx for all of your help flibble

 

[mrflibble]

Ok I tried connecting only two of them, all works properly either in behavioral either post route simulation: to get the correct functionality you must put to '0' the input you don't use as you said and as I did on the first time.

Glad you got it working. And yeah, I misremembered the Z vs 0 for the unused bit.

When using just two carry4 I get all the the connection in the rtl schematic, while using all the carry I need (41) some connections disappear... I found in other forum (I don't know if i can post a link to other forum btw it's the official one) that this is because newer version of ISE have some problem with that and this is confirmed by experience...

If you have a link from something like forums.xilinx.com that is relevant to this thread, I don't think that will be a problem. Hasn't been a problem in the past... I'd certainly be interested in reading it.