Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

false paths and multicycle paths in Digital circuits

Status
Not open for further replies.

spartacus2

Newbie level 6
Joined
Apr 1, 2006
Messages
14
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,459
multi-cycle path and false paths

Hi

I am doing a project on determining the existence of false paths and multicyle paths present in a circuit. Is there is software available for giving this information if the circuit netlist is given?
 

how spyglass check mcp

usually MCP and false paths are specified by the designer before synthesis to Design compiler(synthesis Tool). there are some tools which is able to locate these paths from the RTL. for eg https://www.fishtail-da.com/
 

false paths in digital circuits

DC can provide the check for logical false path. But this only come with DC-Ultra license, and it takes quite some time to run the check.
 

false path digital circuits

I thought that muclticycles paths are very dangerous for a digital system. So I believed that any sinthesys tool is able to detect it and put a warning...
 

digital multicycle path

multicycle-path and false-path only affact when there are combinational loops in your design, or the timing constrain is violated
 

False path is used to find only asynchronous path
Multicycle path is which where the design takes more than one cycle to complete a logic

Din
 

I think Spyglass is there for checking the constraints...i.e the false paths and multicycle paths..It does the check on RTL..
 

SpyGlass-Constraints product can do that, it can check on RTL as well as Gate-Level netlist. But it does not come free and will be sold to Design Companies only.

Regards,
Narayana
 

@ energeticdin :
False path is used to find only asynchronous path

what does this mean ??? ... can u elaborate ????

WBR
Lakshman

Added after 22 minutes:

false path are those which exist in the design but u do not want to report the timing on tht path !!

so in that case u can specify to the tool tht particular path as a "false path" ( the tool still does a timing chk on that path, but doesnt report .. )

e.g : false path can exist between 2 clk domains !!!

MCP are purely design issues ... therz nutin dangerous abt having a MCP !!!

WBR
Lakshman
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top