shaiko
Advanced Member level 5
Hello,
I'm using a 128 to 32 bit FIFO in my Altera Cyclone V SOC design.
Timequest shows a setup violation on 10 lines internal to this IP.
The "Launch Clock" and "Latch Clock" for the failing paths are the same.
However, for some reason I can't locate the failing paths in the RTL viewer.
As if they don't really exist...
What's going on?
I'm using a 128 to 32 bit FIFO in my Altera Cyclone V SOC design.
Timequest shows a setup violation on 10 lines internal to this IP.
The "Launch Clock" and "Latch Clock" for the failing paths are the same.
However, for some reason I can't locate the failing paths in the RTL viewer.
As if they don't really exist...
What's going on?