eye diagram for clock

[surianova]

I have a few Question to ask regarding the digital circuit. Example for clock, do we check the eyediagram for clock and make sure the eye diagram is symentrical ? or we just check the duty cycle for clock to make sure 50 % and ignore the eyediagram? As i know , normally we will check eyediagram for analog circuit but i am not sure about digital circuit. 'This is very important because the clock will be use a reference clock for my PLL. Thanks for all your answer and feedback...

 

[sengyee88]

Normally we generate eye diagram to check jitter, overshoot, undershoot, rise/fall time, mask margin etc. For clock, it is just digital pulses with fast rise/fall time. You will not get much info from the eye diagram.

 

[krashkealoha]

I don't think you are able to generate an eye diagram from a clock signal (1010). The eye diagram is generated from a PRBS signal such as PRBS7 or PRBS23, etc..

For a clock signal the important parameters are rise/fall time, RMS jitter (phase noise), Vout_pp vs. Frequency.

 

[atmjr]

try this link...
www.bertscope.com/Literature/Lit_Requests/info_poster.html

Added after 49 seconds:

how bout this...
**broken link removed**