extraction problem, need help urgently please

[Yashwant]

I designed current source layout having terminal of 10nA and 50nA.I was done LVS and DRC and there is no error. I simulate current source using schematic, it is working perfectly.But When I simulate the same after extraction the result is swaped(10nA----teminal gives 50nA and 50nA terminal gives gives 10nA).I did't get problem exactly.


kindly help me.


tx in advance.

 

[Yanhui]

what is the tool used...

maybe a bug of tool :-D

u can change the name of pins and try again

 

[sharath79]

which tool for lvs u used. It may be a problem with ur layout also . If ur using a diffrential pair the the routings should exactly match then only u will get equal prasitic on both the gates. this may be a problem check this out