Errors in the Layout after DRC

[urn]

Hi,

I am using MOSIS 0.35um process. While doing the layout, after DRC i am getting the following errors.

1) LATI. 3A N-Well PICK-UP to PMOS max space < 20um
2) LATI. 3A P-Well PICK-UP to NMOS max space < 20um

Can anyone help me solving these errors.

Thanks in advance,

 

[dick_freebird]

You need more body ties than you have put down, closer to
the transistor. And you may need to respect some max finger
width rules implicit in such tie-spacing requirements.

 

[leo_o2]

Yes，pls add more N+ contacts for Nwell of PMOS and add more P+ contacts for p-sub of NMOS. For every NMOS/PMOS, it should have body contact within 20um around it.