Errors and warnings when compiling HDL simulation libraries in xilinx ISE 10.1

[mrnithinmr]

Here's a sample of the errors and warnings i get when compiling through the "compile hdl simulation libraries" option..


--> Compiling vhdl unisim library
> Unisim compiled to D:\xilinx\ISE\vhdl\mti_se\unisim
> Log file D:\xilinx\ISE\vhdl\mti_se\unisim\cxl_unisim.log generated
> Library mapping successful, setup file(s) modelsim.ini updated

compxlib[unisim]: No error(s), 3 warning(s)

--> Compiling vhdl unimacro library
> unimacro compiled to D:\xilinx\ISE\vhdl\mti_se\unimacro
> Log file D:\xilinx\ISE\vhdl\mti_se\unimacro\cxl_unimacro.log generated
> Library mapping successful, setup file(s) modelsim.ini updated

compxlib[unimacro]: No error(s), no warning(s)

--> Compiling vhdl simprim library
> Simprim compiled to D:\xilinx\ISE\vhdl\mti_se\simprim
> Log file D:\xilinx\ISE\vhdl\mti_se\simprim\cxl_simprim.log generated
> Library mapping successful, setup file(s) modelsim.ini updated

compxlib[simprim]: No error(s), 989 warning(s)

--> Compiling vhdl XilinxCoreLib library
> XilinxCoreLib compiled to D:\xilinx\ISE\vhdl\mti_se\XilinxCoreLib
> Log file D:\xilinx\ISE\vhdl\mti_se\XilinxCoreLib\cxl_XilinxCoreLib.log generated
> Library mapping successful, setup file(s) modelsim.ini updated

compxlib[XilinxCoreLib]: No error(s), 124 warning(s)
MTI => Model Technology ModelSim SE vcom 6.4b Compiler 2008.11 Nov 14 2008

--> Compiling vhdl secureip(secureip) library
> secureip Secure-IPs compiled to D:\xilinx\ISE\vhdl\mti_se\secureip
> Log file D:\xilinx\ISE\vhdl\mti_se\secureip\cxl_secureip.log generated
> Library mapping successful, setup file(s) modelsim.ini updated

compxlib[secureip]: No error(s), no warning(s)

--> Compiling vhdl smartmodel(unisim) library
> use -smartmodel_setup switch in case you want to configure
the modelsim.ini for smart model usage (SWIFT Interface)
> Unisim Smart-Models compiled to D:\xilinx\ISE\vhdl\mti_se\unisim
> Log file D:\xilinx\ISE\vhdl\mti_se\unisim\cxl_smartmodel.log generated
> Library mapping successful, setup file(s) modelsim.ini updated

compxlib[smartmodel]: No error(s), no warning(s)

--> Compiling vhdl smartmodel(simprim) library
> use -smartmodel_setup switch in case you want to configure
the modelsim.ini for smart model usage (SWIFT Interface)
> Simprim Smart-Models compiled to D:\xilinx\ISE\vhdl\mti_se\simprim
> Log file D:\xilinx\ISE\vhdl\mti_se\simprim\cxl_smartmodel.log generated
> Library mapping successful, setup file(s) modelsim.ini updated

compxlib[smartmodel]: 14 error(s), 306 warning(s)

Log file (compxlib.log) generated.


Process "Compile HDL Simulation Libraries" failed

 

[TrickyDicky]

I suggest you read the errors and fix them.

 

[mrflibble]

XD

My first thoughts: well now that's a bit cynical Mr TrickyDicky.

My second collection of thoughts (after reading the OP a bit better): wut? 14 errors when running compxlib. I never got that when I ran things on an normally configured setup.

So after that ... yeah, read the errors and fix things!! So TrickyDicky's reply turned out to be perfectly tuned to reality. Read Yo Log Messages And Stuffs. The compxlib.log file shall be a treasure trove of clues for you to explore dear mrnithinmr. Adventure awaits!

 

[mrnithinmr]

I have compiled hdl simulation library for modelsim SE PLUS 6.4b.

I have compiled it for an example_design for ethernet mac generated using ipcore generator 10.1

plz help me.............

these are some of the warnings.....


** Warning: [6] D:\xilinx\ISE\vhdl\src\simprims\simprim_VITAL_mti. vhd(7927): (vcom-1288) VITAL timing generic "tisd_gsr_c0" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### D:\xilinx\ISE\vhdl\src\simprims\simprim_VITAL_mti. vhd(7928): tisd_GSR_C1 : VitalDelayType := 0.000 ns;
** Warning: [6] D:\xilinx\ISE\vhdl\src\simprims\simprim_VITAL_mti. vhd(7928): (vcom-1288) VITAL timing generic "tisd_gsr_c1" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### D:\xilinx\ISE\vhdl\src\simprims\simprim_VITAL_mti. vhd(7935): tpd_GSR_Q : VitalDelayType01 := (0.000 ns, 0.000 ns);
** Warning: [6] D:\xilinx\ISE\vhdl\src\simprims\simprim_VITAL_mti. vhd(7935): (vcom-1288) VITAL timing generic "tpd_gsr_q" port specification "gsr" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### D:\xilinx\ISE\vhdl\src\simprims\simprim_VITAL_mti. vhd(7943): tpw_GSR_posedge : VitalDelayType := 0.000 ns;

** Warning: [6] D:\xilinx\ISE\vhdl\src\simprims\simprim_VITAL_mti. vhd(149508): (vcom-1287) VITAL timing generic "tisd_d3" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### D:\xilinx\ISE\vhdl\src\simprims\simprim_VITAL_mti. vhd(149509): tisd_D4 : VitalDelayType := 0.000 ns;
** Warning: [6] D:\xilinx\ISE\vhdl\src\simprims\simprim_VITAL_mti. vhd(149509): (vcom-1287) VITAL timing generic "tisd_d4" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### D:\xilinx\ISE\vhdl\src\simprims\simprim_VITAL_mti. vhd(149510): tisd_D5 : VitalDelayType := 0.000 ns;
** Warning: [6] D:\xilinx\ISE\vhdl\src\simprims\simprim_VITAL_mti. vhd(149510): (vcom-1287) VITAL timing generic "tisd_d5" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### D:\xilinx\ISE\vhdl\src\simprims\simprim_VITAL_mti. vhd(149511): tisd_D6 : VitalDelayType := 0.000 ns;

 

[mrflibble]

Warnings are sometimes just that, warnings. Chances are your simulation "works" despite those warnings.