Error when simulating a program in Synopsys

[triump.ar]

hi, i m trying to simulate the prgrm using synopsys...i m using dealy logic..wtever is the present output it will be the output of the next register at the next clock....
wts the error i m not geting....some1 can help me....i want to use synopsys tool for this


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity filt18 is
port
(
clk1:in std_logic; --std logic is define standard which will synthesisble
y2: in std_logic_vector (12 downto 0); --airthmetic operation cannot be done using bit vector or other,std_logic_vector is necessary
y3: out std_logic_vector (12 downto 0));
end filt18;

architecture Behavioral of filt18 is

type data_bus is array (integer range <>) of std_logic_vector (12 downto 0);
signal x_d: data_bus(0 to 18) ;
begin

process (clk1,y2)--this process will do shifting
begin
x_d(0)<=y2;
if (clk1='1' and clk1'event) then
for i in 1 to 18 loop
x_d(i) <= x_d(i-1);
end loop;
end if;

end process;

y3<=x_d(18);

end Behavioral;

 

[FvM]

Re: synopsys prgm error

Why don't you post the error message and the respective line of code?