Error to run simv when using VCS to simulate both Verilog and Vhdl

[wbr]

I can use vcs-mx-2016 to simulate verilog or vhdl.
When I tyied to simulate vhdl and verilog in the same project, I was able to compile file with vhdlan and vlogan. However I got a error that event debug mode not supported, when I was excuting the generated file simv.
"Error-[SC_RUNNING_PCODE] event debug mode not supported
You are running '1' design unit(s) : 'DEFAULT.FULL_ADDER(SYNTH)' in event
debug mode which is not supported in this release.
Please contact Synopsys support for further assistance."