neural84
Newbie level 4
Hey...
I'm going to implement a neural network by FPGA.
When i running the xise file that produced by matlab in synthesis message it show 1 error and 4 warning.
I hope some body help me to solve them.
thank you.
WARNING : HDLCompilers:259 - "../IW_1_1.v" line 48 Connection to input port 'w' does not match port size.
WARNING : HDLCompilers:259 - "../IW_1_1.v" line 59 Connection to input port 'w' does not match port size.
WARNING : HDLCompilers:259 - "../IW_1_1.v" line 70 Connection to input port 'w' does not match port size.
WARNING : HDLCompilers:259 - "../Layer_2.v" line 70 Connection to input port 'n' does not match port size.
ERROR : Xst:2228 - "../Layer_1.v" line 41: Unsupported Real variable.
I'm going to implement a neural network by FPGA.
When i running the xise file that produced by matlab in synthesis message it show 1 error and 4 warning.
I hope some body help me to solve them.
thank you.
WARNING : HDLCompilers:259 - "../IW_1_1.v" line 48 Connection to input port 'w' does not match port size.
WARNING : HDLCompilers:259 - "../IW_1_1.v" line 59 Connection to input port 'w' does not match port size.
WARNING : HDLCompilers:259 - "../IW_1_1.v" line 70 Connection to input port 'w' does not match port size.
WARNING : HDLCompilers:259 - "../Layer_2.v" line 70 Connection to input port 'n' does not match port size.
ERROR : Xst:2228 - "../Layer_1.v" line 41: Unsupported Real variable.