error in vhdl code,please check it?

[abhineet22]

after running this code the error is bad synchronous description..........
can any one help me....

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity accumulator is
port( data : inout std_logic_vector(7 downto 0);
rd_wr : in std_logic; --0=read,1=write
clock : in std_logic;
reset : in std_logic
);
end accumulator;

architecture rtl of accumulator is
signal temp_data_in:std_logic_vector(7 downto 0);
signal temp_data_out:std_logic_vector(7 downto 0);

component byte_register is
port (
Reset : in std_logic;
Enable : in std_logic;
Clock : in std_logic;
Datain : in std_logic_vector(7 downto 0);
Dataout : out std_logic_vector(7 downto 0) );
end component;
begin
acc: byte_register port map(reset,rd_wr,clock,temp_data_in,temp_data_out);
process(clock,reset)
begin
if clock'event and clock='1'and reset='0'then
if rd_wr='0'then
data<=temp_data_out;
else
temp_data_in<=data;
end if;
else
data<=temp_data_out;
end if;
end process;
end rtl;



library iEEE;
use iEEE.std_logic_1164.all;

entity byte_register is
port (
Reset : in std_logic;
Enable : in std_logic;
Clock : in std_logic;
Datain : in std_logic_vector(7 downto 0);
Dataout : out std_logic_vector(7 downto 0) );
end byte_register;

architecture behav of byte_register is

begin
process(Clock,Reset, Datain)
begin
if(Reset='1') then
Dataout<="00000000";
elsif(Reset='0' and Enable = '1' and clock = '1' and clock'event) then
Dataout<=Datain;
end if;
end process;
end behav;

 

[sesl33]

process(clock,reset)
begin
if clock'event and clock='1'and reset='0'then
if rd_wr='0'then
data<=temp_data_out;
else
temp_data_in<=data;
end if;
else
data<=temp_data_out;
end if;
end process;
end rtl;

I think that the problem is with 2 parts. I will try to explain the first part.
The problem is that you are "confusing" the compiler when you lump lots of conditions in the process statement.
i.e. --> if clock'event and clock='1'and reset='0'then

I assume that you want a circuit with synchronous reset.
Typically we isolate the edge triggering and the reset signal.

i.e.
if (clock'event and clock = '1') then
if (reset = '1') then
data<=temp_data_out;
elsif (rd_wr = '0') then
data<=temp_data_out;
else
temp_data_in<=data;
end if;
end if;

Added after 6 minutes:

architecture behav of byte_register is

begin
process(Clock,Reset, Datain)
begin
if(Reset='1') then
Dataout<="00000000";
elsif(Reset='0' and Enable = '1' and clock = '1' and clock'event) then
Dataout<=Datain;
end if;
end process;
end behav;

The second part is of the same argument with the first.
i.e. --> elsif(Reset='0' and Enable = '1' and clock = '1' and clock'event) then

This time, it seemed that you want an asynchonrous reset.
Prehaps, you can change that to:

process(Clock,Reset, Datain, Enable)
begin
if(Reset='1') then
Dataout<="00000000";
elsif(clock = '1' and clock'event) then
if (Enable = '1') then
Dataout<=Datain;
end if;
end if;
end process;

PS: you have forgotten to add the Enable signal in the process list

 

[zcg]

"if clock'event and clock='1'and reset='0'then "

what's this? what kind of circuit do you expect it will be synthesized?

 

[koppolu1981]

Hi abhineet,
The error is because u have clubbed the structural code and behavioural code in the same architecture. Try to take the behavioural code out and write the same as a different module(entity).
Then connect the byte_register module and this module using structural model that will work out.....

 

[bajahaya]

Maybe this could be one possible solution


read_write :
process(clock,reset)
begin
if reset = '1' then
temp_data_out <= (others => '0');
elsif rising_edge(clk) then
if rd_wr = '0' then
data <= temp_data_out;
else
temp_data_in<=data;
end if;
end if;
end process read_write;