moisiad
Member level 4
Hi all
In the sample and hold stage of a 1.5 bit pipeline ADC converter, when i get the Vin-Vout characteristic of the stage (the one with the triangles), i have noticed that the whole characteristic is shifted up by 60mV.
I suppose that this is the systematic offset error which is not so critical (according to some books ). Am i wright? What are possible sources of this error?
("Sunking" i am waiting your help )
Thanks
In the sample and hold stage of a 1.5 bit pipeline ADC converter, when i get the Vin-Vout characteristic of the stage (the one with the triangles), i have noticed that the whole characteristic is shifted up by 60mV.
I suppose that this is the systematic offset error which is not so critical (according to some books ). Am i wright? What are possible sources of this error?
("Sunking" i am waiting your help )
Thanks