Error in simulation of comparator in tanner eda

[hulk789]

Can somebody help me out debug the issue of non convergence.

error

T-Spice - Tanner SPICE
T-Spice - Tanner SPICE
Version 14.11
Network license
Product Release ID: T-Spice Win32 14.11.20090811.05:10:58
Copyright © 1988-2009 Tanner EDA

	Parsing "C:\Users\RAJUCH~1\AppData\Local\Temp\Comparator1.sp"
	Including "C:\Users\Raju Chaudhari\Documents\Tanner EDA\Tanner Tools v14.1\L-Edit and LVS\LVS\SPR_Core\hp05.md"
Loaded MOSLevel3 model library, SPICE Level 3 MOSFET revision 1.0

General options:
        threads = 4



 Device and node counts:
            MOSFETs - 9                 MOSFET geometries - 2       
               BJTs - 0                             JFETs - 0       
            MESFETs - 0                            Diodes - 0       
         Capacitors - 2                         Resistors - 0       
          Inductors - 0                  Mutual inductors - 0       
 Transmission lines - 0        Coupled transmission lines - 0       
    Voltage sources - 2                   Current sources - 2       
               VCVS - 0                              VCCS - 0       
               CCVS - 0                              CCCS - 0       
   V-control switch - 0                  I-control switch - 0       
      Macro devices - 0                 Verilog-A devices - 0       
        Subcircuits - 0              Subcircuit instances - 0       
  Model Definitions - 2                   Computed Models - 2       
  Independent nodes - 7                    Boundary nodes - 3       
        Total nodes - 10      

	Opening output file "C:\Users\RAJUCH~1\AppData\Local\Temp\Comparator1.out"
Warning : Newton solver has failed due to extremely large node voltages.
        : If the circuit has very high gain and extremely large voltages (>1000V) are expected,
        : then you may use '.option vmax=0' to disable this check.
Conventional DC operating point computation failed.
Gmin stepping failed
Final gmin value = 1e-006, dcstep = 100
Source stepping failed at   0.00% rampup
Multi-rate source stepping failed at  33.33% rampup due to source inp
Pseudotransient analysis at 0% completion
Pseudotransient analysis failed
Fatal Error : DC operating point non-convergence


Parsing                      0.01 seconds
Setup                        0.01 seconds
DC operating point           0.64 seconds
Transient Analysis           0.00 seconds
Overhead                     9.29 seconds
-----------------------------------------
Total                        9.94 seconds

Simulation failed	with  1 Warning  1 Fatal Error

Netlist

********* Simulation Settings - General section *********

********* Simulation Settings - Parameters and SPICE Options *********

*-------- Devices: SPICE.ORDER > 0 --------
CCapacitor_1 Outm Gnd  1p  
CCapacitor_2 Outp Gnd  1p  
MNMOS_1 N_2 Inp N_1 N_1 NMOS W=2.5u L=600n AS=2.25p PS=6.8u AD=2.25p PD=6.8u  
MNMOS_2 N_4 Inm N_1 N_1 NMOS W=2.5u L=600n AS=2.25p PS=6.8u AD=2.25p PD=6.8u  
MNMOS_3 N_1 LATP Gnd Gnd NMOS W=2.5u L=600n AS=2.25p PS=6.8u AD=2.25p PD=6.8u  
MNMOS_4 Outp Outm N_4 N_4 NMOS W=2.5u L=600n AS=2.25p PS=6.8u AD=2.25p PD=6.8u  
MNMOS_5 Outm Outp N_2 N_2 NMOS W=2.5u L=600n AS=2.25p PS=6.8u AD=2.25p PD=6.8u  
MPMOS_1 Outm Outp Vdd Vdd PMOS W=7.5u L=600n AS=6.75p PS=16.8u AD=6.75p PD=16.8u  
MPMOS_2 Outp Outm Vdd Vdd PMOS W=7.5u L=600n AS=6.75p PS=16.8u AD=6.75p PD=16.8u  
MPMOS_3 Outp LATP Vdd Vdd PMOS W=7.5u L=600n AS=6.75p PS=16.8u AD=6.75p PD=16.8u  
MPMOS_4 Outm LATP Vdd Vdd PMOS W=7.5u L=600n AS=6.75p PS=16.8u AD=6.75p PD=16.8u  

********* Simulation Settings - Analysis section *********
.tran 1n 800n
.include "C:\Users\Raju Chaudhari\Documents\Tanner EDA\Tanner Tools v14.1\L-Edit and LVS\LVS\SPR_Core\hp05.md"

.print tran v(Outp,gnd) v(Outm,gnd) v(LATP,gnd) v(Inp,gnd) v(Inm,gnd)
vdd Vdd gnd DC 5
inp Inp gnd DC 3.0
inm Inm gnd DC 4.0
Vclk LATP gnd DC 0.0
********* Simulation Settings - Additional SPICE commands *********

.end

 

[erikl]

Vclk LATP gnd DC 0.0

Where's your test setup? I can't see any stimulus.

 

[dick_freebird]

It's a clocked comparator design but the clock does nothing.
Just sits there with the two LAT switches killing the load.
But why this would not simply converge to a useless state
I do not see offhand.

Probably time for you to try some of the usual tricks. And
I'd bet you can find those by trying.