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From the error message shown by the IC compiler, it seems that your core utilization is over 100% and thus IC compiler can't continue the placement. Maybe you can solve this by lower utilization rate when "specify the floorplan" or "initialize the floorplan."
Could you talk about your design functionality ?
It helps us with the estimation of scale/property of the design.
For example, the design is too small such that room for improvement with 0.3*area is also small.
I guess so. 4-to-1 MUX is so small that it's just composed of several gates.
The room for adding more optimization device is 0.3*(cell area) which is also small.
Could you tell me which the stage is when the error occurs ? floorplanning ? powerplanning ? placement ? CTS ? routing ? manufacturing ?
To be more specifically, it's clues that we have to know which devices may be added.
Once the optimized device is supposed to add into the design, the remaining room is seemed to be insufficient.