rafimiet
Member level 5
I try to simulate a design with the test bench as follows:
I get the following errors:
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE std.textio.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values USE ieee.numeric_std.ALL; ENTITY fsm_tbw IS END fsm_tbw; ARCHITECTURE behavior OF fsm_tbw IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT FSM_all PORT( rst : IN std_logic; clk : IN std_logic; i : IN std_logic_vector(7 downto 0); out_en : OUT std_logic; y : OUT std_logic_vector(10 downto 0) ); END COMPONENT; --Inputs signal rst,out_en : std_logic := '0'; signal clk,endoffile : std_logic := '0'; signal i : std_logic_vector(7 downto 0) := (others => '0'); --Outputs signal y : std_logic_vector(10 downto 0); -- Clock period definitions constant clk_period : time := 10 ns; -- TEXT FILE -- FILE g: TEXT OPEN WRITE_MODE IS "trans.txt"; FILE f: TEXT OPEN READ_MODE IS "orig.txt"; BEGIN mapping: FSM_all port map (rst, clk,i,out_en,y); -- Clock process definitions rst <= '0'; clk <= NOT clk AFTER 10ns; -- Stimulus process reading: process VARIABLE l: LINE; VARIABLE good_value : BOOLEAN; VARIABLE pixl1 : INTEGER RANGE 0 TO 255; begin wait until clk = '1' and clk'event; if (not endfile(f)) then READLINE(f,l); READ(l,pixl1,good_value); i <= std_logic_vector(to_signed(pixl1,8)); else endoffile <='1'; --set signal to tell end of file read file is reached. end if; end process reading; writing: process VARIABLE m: LINE; VARIABLE good_value : BOOLEAN; VARIABLE pixl3 : INTEGER RANGE 0 TO 255; variable count : INTEGER RANGE 0 TO 255; begin wait until clk = '1' and clk'event; if out_en = '1' then if count <= 262144 then pixl3 := to_integer(signed(y)); WRITE(m,pixl3); WRITELINE(g,m); --set signal to tell end of file read file is reached. count := count + 1; end if; end if; end process writing; END behavior;
I get the following errors:
The same testbench works fine in ISIM (used in ISE 14.4). Can anybody tell me what to do?launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'fsm_tbw' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in 'D:/Local Disk/PHD_WORK/xilinx_projects/vivado_learning_project/vivado_learning_project.sim/sim_1/behav'
"xvhdl -m64 --relax -prj fsm_tbw_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Local Disk/PHD_WORK/xilinx_projects/vivado_learning_project/vivado_learning_project.srcs/sources_1/new/FSM_all.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity FSM_all
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Local Disk/PHD_WORK/xilinx_projects/vivado_learning_project/vivado_learning_project.srcs/sim_1/new/fsm_tbw.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity fsm_tbw
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Local Disk/PHD_WORK/xilinx_projects/vivado_learning_project/vivado_learning_project.sim/sim_1/behav'
Vivado Simulator 2015.4
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2015.4/bin/unwrapped/win64.o/xelab.exe -wto b83cae4e17f842aa960b1ce68e23e5d4 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot fsm_tbw_behav xil_defaultlib.fsm_tbw -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package ieee.std_logic_1164
Compiling package std.textio
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.FSM_all [\FSM_all(3,256,8,16,11)\]
Compiling architecture behavior of entity xil_defaultlib.fsm_tbw
Built simulation snapshot fsm_tbw_behav
****** Webtalk v2015.4 (64-bit)
**** SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
**** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
source D:/Local -notrace
invalid command name "Common"
while executing
"Common 17-165"
invoked from within
"ERROR: [Common 17-165] Too many positional options when parsing 'projects/vivado_learning_project/vivado_learning_project.hw/webtalk/labtool_webtalk.l..."
(file "D:/Local" line 1)
INFO: [Common 17-206] Exiting Webtalk at Wed Sep 13 12:11:12 2017...
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Local Disk/PHD_WORK/xilinx_projects/vivado_learning_project/vivado_learning_project.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
with args "fsm_tbw_behav -key {Behavioral:sim_1:Functional:fsm_tbw} -tclbatch {fsm_tbw.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.4
ERROR: File orig.txt could not be opened
on HDL file D:/Local Disk/PHD_WORK/xilinx_projects/vivado_learning_project/vivado_learning_project.srcs/sim_1/new/fsm_tbw.vhd line 67
ERROR: [Simtcl 6-50] Simulation engine failed to start: The Simulation shut down unexpectedly during initialization.
Please see the Tcl Console or the Messages for details.
ERROR: [USF-XSim-62] 'simulate' step failed with errors. Please check the Tcl console or log files for more information.
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:20 . Memory (MB): peak = 754.379 ; gain = 35.941