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Error (10028): Can't resolve multiple constant drivers for net "D0" at clk_div_librar

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implementation on DE2 not giving exact results

I am writing a code for generation of various frequency range from 1Mhz to 1 hz from an input 50mhz clk.
The full code is as below.


Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;


entity clk_div_librarymodule is 
      port (
            clock_50mhz : in std_logic;
            sw          : in std_logic; --sw[0]
             clock_1hz: out std_logic;
            clock_100khz,
            clock_10khz,
            clock_1khz,
            clock_100hz,
            clock_10hz,
            clock_1mhz      :buffer std_logic;
            ledg0,ledg1,ledg2,ledg3,ledg4,ledg5,ledg6        : out std_logic  --ledg[7]
           );
end entity clk_div_librarymodule;

architecture a_clk_div_librarymodule of clk_div_librarymodule is 
 signal D0,D1,D2,D3,D4,D5,D6 :std_logic;
 signal count_50mhz,count_1mhz,count_100khz,count_10khz,count_1khz,count_100hz,count_10hz,count_1hz : std_logic_vector(27 downTO 0);
         begin
 ------------------------------------------------------------
 process(clock_50mhz,sw)
  begin
       
        if (sw='1') then
            count_50mhz<=X"0000000";
            D0<='0';
        elsif (clock_50mhz'event and clock_50mhz='1') then
            count_50mhz<= count_50mhz+1;
            
        if( count_50mhz < X"2FAF080" ) then
           ledg0<='1';
           D0<= not D0;
           
        elsif (count_50mhz > X"2FAF080") then
           if (count_50mhz < X"5F5E0FF") then
               ledg0<='0';
               
           else 
               count_50mhz <=X"0000000";
         end if;
         end if;
         end if;
         clock_1hz<=D0;
         
         end process;
  ----------------------------------------------------- 
  process(clock_50mhz,sw)
  begin
       
        if (sw='1') then          ------------------------[B][U]<ERROR HERE>[/U][/B]
            count_1mhz<=X"0000000";
            D1<='0';
        elsif (clock_50mhz'event and clock_50mhz='1') then
            count_1mhz<= count_1mhz+1;
            
        if( count_1mhz < X"32" ) then
           ledg1<='1';
           D1<=NOT D1;
        elsif (count_1mhz > X"32") then
           if (count_1mhz < X"64") then
               ledg1<='0';
           else 
               count_1mhz <=X"0000000";
         end if;
         end if;
         end if;
         
         clock_1mhz<= D1;
         
         end process;
 ----------------------------------------------------- 
 
  process(clock_50mhz,sw)
  begin
       
        if (sw='1') then
            count_100khz<=X"0000000";
            D2<='0';
        elsif (clock_50mhz'event and clock_50mhz='1') then
            count_100khz<= count_100khz+1;
            
        if( count_100khz < X"1F4" ) then
           ledg2<='1';
           D2<= NOT D2;
        elsif (count_100khz > X"1F4") then
           if (count_100khz < X"3E8") then
               ledg2<='0';
           else 
               count_100khz <=X"0000000";
         end if;
         end if;
         end if;
          clock_100khz<=D2;
         
         end process;
-----------------------------------------------------

  process(clock_50mhz,sw)
  begin
       
        if (sw='1') then
            count_10khz<=X"0000000";
            D3<='0';
        elsif (clock_50mhz'event and clock_50mhz='1') then
            count_10khz<= count_10khz+1;
            
        if( count_10khz < X"1388" ) then
           ledg3<='1';
           D3<= NOT D3;
        elsif (count_10khz > X"1388") then
           if (count_10khz < X"2710") then
               ledg3<='0';
           else 
               count_10khz <=X"0000000";
         end if;
         end if;
         end if;
         clock_10khz<= D3;
         
         end process;   
         
 ----------------------------------------------------- 
  process(clock_50mhz,sw)
  begin
       
        if (sw='1') then
            count_1khz<=X"0000000";
            D4<='0';
        elsif (clock_50mhz'event and clock_50mhz='1') then
            count_1khz<= count_1khz+1;
            
        if( count_1khz < X"C350" ) then
           ledg4<='1';
           D4<= NOT D4;
        elsif (count_1khz > X"C350") then
           if (count_1khz < X"186A0") then
               ledg4<='0';
           else 
               count_1khz <=X"0000000";
         end if;
         end if;
         end if;
        -- clock_1khz<='D4';
         end process;          
         
----------------------------------------------------------

  process(clock_50mhz,sw)
  begin
       
        if (sw='1') then
            count_100hz<=X"0000000";
            D5<='0';
        elsif (clock_50mhz'event and clock_50mhz='1') then
            count_100hz<= count_100hz+1;
            
        if( count_100hz < X"7A120" ) then
           ledg5<='1';
           D5<= NOT D5;
        elsif (count_100hz > X"7A120") then
           if (count_100hz < X"F4240") then
               ledg5<='0';
           else 
               count_100hz <=X"0000000";
         end if;
         end if;
         end if;
         clock_100hz<=D5;
         end process;
 ----------------------------------------------------- 
  process(clock_50mhz,sw)
  begin
       
        if (sw='1') then
            count_10hz<=X"0000000";
            D6<='0';
        elsif (clock_50mhz'event and clock_50mhz='1') then
            count_10hz<= count_10hz+1;
            
        if( count_10hz < X"4C4B40" ) then
           ledg6<='1';
           D6<= NOT D6;
        elsif (count_10hz > X"4C4B40") then
           if (count_10hz < X"989680") then
               ledg6<='0';
           else 
               count_10hz <=X"0000000";
         end if;
         end if;
         end if;
         clock_10hz<=D6;
         end process;        
         
end a_clk_div_librarymodule;

The code is not giving desired output on DE2 board. The led are not glowing as they should.
Please do mention if you require any other inputs.

Please troubleshoot the same.
Thankyou.
 
Last edited:

Re: Error (10028): Can't resolve multiple constant drivers for net "D0" at clk_div_li

The error you are getting is suggesting you are trying to drive D0 from more than 1 process, which appears not to be the case. You can only assign signals/outputs inside 1 process.

Why do you have all of the generated clocks as buffers? you do not read them internally, so why not set them as out ports?

A second point - why have you got all the clock signals assigned inside the processes? when you simulate, this will have the effect of delaying the outputs by a further clock signal, or only change when the "sw" signal changes. But then in hardware it will not behave the same way as it will just wire the clock signal directly to Dn. Move this assignment statement outside of the process.
 

Re: Error (10028): Can't resolve multiple constant drivers for net "D0" at clk_div_li

hello sir,
Thanks for your reply. I will implement your suggestions and get back to you in few hours.
 

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