suling
Junior Member level 3
Had started to learn to write veriloga. However, had some problems for the following. Would appreciate if someone can help.
1) Is there any limit on the number of buses to be define for a module? Had added in 4 buses with a<1:0>, b<2:0>, c<2:0> and d<5:0> and syntax error occurs, showing "Maximum allowable errors exceeded". However, the error disappear when remove c and d bus.
2) How to pass parameter to each bus? Are the following codes OK?
always @(a)
case (a)
2'b00: gain=25;
2'b01: gain=20;
2'b10: gain=15;
2'b11: gain=20;
endcase
Please advise.
1) Is there any limit on the number of buses to be define for a module? Had added in 4 buses with a<1:0>, b<2:0>, c<2:0> and d<5:0> and syntax error occurs, showing "Maximum allowable errors exceeded". However, the error disappear when remove c and d bus.
2) How to pass parameter to each bus? Are the following codes OK?
always @(a)
case (a)
2'b00: gain=25;
2'b01: gain=20;
2'b10: gain=15;
2'b11: gain=20;
endcase
Please advise.