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ECO is one of the technique through which u can change the buffer or u can upsize or downsize the buffer if u want...........
Once u do timing optimization ur timing may not meet smetimes bcz of some component like assume tht ur buffer fanout is very high which is exceedng ur constraint so wth the help of this engineering change order u can resize it or if u want u can move it u can do many things with ECO...
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When you are done with the whole design flow (from rtl to gdsII) on a design and at the last moment you get to know that your design needs some more fine tuning and fixing. At this point, nobody will go through the whole design flow instead the designer will use ECO technique. With this technique, you will only focus on that part of the design which needs fixing(it may be upsizing/downzing of inv/buffer or maybe change in a couple of routes.) without disturbing the already stable part of the design.
Is there a concept of placing some cells like dummy cells in the design which can be replaced to accomadate last minute changes in eco.........................
wat is the procedure followed to place dummy cells in the core. Hw do we expect the location where we need to perform eco while placing the dummy cells.
Almost Every IC after tapeout do ECO.
First Cut work is very hard.
1)You must prepare dummy cells when first tapeout.
2)spread your dummy cells when APR.
3)ECO automatically find your nearest spare cell to replace your added cell.
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