encounter to icfb : difference in number of pmos and nmos from schematic to layout

[lsqm]

I created the layout of my design using encounter and then imported it to cadence icfb. When I do the LVS check, the netlist matches but the number of pmos and nmos in schematic and that in layout are different. What might be causing this problem ? and how can LVS match when the number of transistors are different?