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Signal Electromigration results from an increase in current density caused by the use of smaller line widths and higher operational speeds in IC Designs. It can lead to shorts or opens due to metal ion displacement caused by the flow of electrons.
Resolving EM violations:
1. Load signal EM constraints in the design library. These contain the library specific current-density thresholds for each metal layer in your design.
2. Verify the EM constraints
3. Verify the current unit defined in the design library.
4. Load the net switching information to perform accurate EM analysis. The more frequently a net switches, the more susceptible it is to EM. To load the net switching activity, either read in a SAIF (Switching activity Interchange Format) file or annotate the switching activity information on the design nets.
5. Update the timing so that the tool can calculate the slew rate on each output pin and thereby determine the current density of each wire and via.
6. Perform EM analysis.
7. The PnR tool will generate a repair file during the analysis. This file defines the variable routing rules such as width and contact constraints for those nets that violate the current constraints.
8. Source the repair file and reroute the design.
This method might vary across different PnR tools. The one described above is for Synopsys ICC.
Causes of EM violations are
1. In adequate metal widths use and skinny metal routing
2. Insufficient numbers of VIA's
3. Metal/VIA current carrying capability of used for power.signal routing like Thick and Thin metals in a tech.
4. Improper POWER BUS plan or POWER GRID plan
5. Not considering the peak to peak current in signal
6. Inaccurate EM numbers due to non settled signal sweep etc
To fix them,
1.Select proper and Number of Metals/VIA's
2. Do proper power plan
3. Use parallel metals or metal stacking.
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