Eight channel pulse generation using DATA and address bus

[anee_anil]

Hi all,

16 bit data bus from external source gives the PRT, PW, Repetition time and delay.
Address bus specifies the 6 bit value which holds the address of the PRT, PW and Repetition and
delay .
when enable is high the CPLD will start reading the data based on the addresses and stores it in a
variable. When enable is low and start is high then the data from the variables are fetched and
based on the data, signal is generated.
The output of eight signals should simultaneously work for different inputs given
PRT : Pulse Repetition Time
PW : Pulse width

Here is my code that gives PRT and Pw. how to implement repetition and delay in the same code.


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use work.my_package.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pulse_rep is
port(data_bus : in std_logic_vector(15 downto 0);
addr_bus : in std_logic_vector(5 downto 0);
clk : in std_logic;
en : in std_logic;
start : in std_logic;
data_out0, data_out1, data_out2, data_out3, data_out4, data_out5, data_out6, data_out7 : out std_logic);
end pulse_rep;

architecture Behavioral of pulse_rep is
signal addr : integer range 0 to 32; -- address in integer numbers
signal rep_int : integer range 0 to 100; -- Repetition in integers
signal clkout1, clkout2 : std_logic;
signal PRT, PW, REP, DELAY : std_logic_vector(15 downto 0);
signal count1, count2 : std_logic_vector(15 downto 0) := "0000000000000000";
signal temp : std_logic_vector(15 downto 0);
type vector_array is array(0 to 3) of
std_logic_vector(15 downto 0);
signal memory : vector_array; -- momory 0 to 3 of 16 bit each
begin
process(clk, en)
variable temp3 : integer range 0 to 32;
variable temp4 : integer range 0 to 100;
begin
temp3 := 0;
if en = '1' then
if clk'event and clk = '1' then
memory(addr) <= data_bus; -- allocating incoming data to the memory
end if;
for i in addr_bus'range loop -- address bus of
if (addr_bus(i) = '1') then -- std_logic_vector
temp3 := 2*temp3 + 1; -- to
else -- integer
temp3 := 2*temp3; -- conversion
end if; --
end loop;
addr <= temp3;
end if;

--for i in REP'range loop -- Repetition of
--if (REP(i) = '1') then -- std_logic_vector
--temp4 := 2*temp4 + 1; -- to
--else -- integer
--temp4 := 2*temp4; -- conversion
--end if; --
--end loop;
--rep_int <= temp4;

PRT <= memory(0);
PW <= memory(1);
REP <= memory(2);
DELAY <= memory(3);
end process;

process(clk, en, start)

variable temp1, temp2 : std_logic_vector(15 downto 0);
begin
--if (start = '1' and en = '0') then
if (clk'event and clk = '1' ) then

temp2 := prt;
clkout1 <= '1';
count1 <= count1 + 1;
if(delay = count1) then

end if;
if(temp2 = count1) then
count1 <= "0000000000000000";
end if;
if(count1 <= pw) then
temp1 := pw;
clkout2 <= '1';
count2 <= count2 + 1;
if(temp1 = count2) then
count2 <= "0000000000000000";
clkout2 <= '0';
end if;
else
clkout2 <= '0';
end if;
end if;
--end if;
data_out0 <= clkout1 and clkout2;

end process;
end Behavioral;

Thanks in advance. Hoping for positive reply