s3034585
Full Member level 4
hi
can any one tell me what is the effect of removing the signals from the sensitivity list in a vhdl code. below is the code for it.
intially only signal a is mentioned in the sensitvity list and then later both a and b are mentioned in the sensitivity list. Can any one tell me the diff on c output and the hardware generated in both the cases.
Thanks
entity trial is
Port ( a : in std_logic;
b : in std_logic;
c : out std_logic);
end trial;
architecture Behavioral of trial is
begin
process (a)
begin
if (a ='1' and b = '0') or (a = '0' and b = '1' )then
c<= '1';
else
c<= '0';
end if;
end process;
end Behavioral;
can any one tell me what is the effect of removing the signals from the sensitivity list in a vhdl code. below is the code for it.
intially only signal a is mentioned in the sensitvity list and then later both a and b are mentioned in the sensitivity list. Can any one tell me the diff on c output and the hardware generated in both the cases.
Thanks
entity trial is
Port ( a : in std_logic;
b : in std_logic;
c : out std_logic);
end trial;
architecture Behavioral of trial is
begin
process (a)
begin
if (a ='1' and b = '0') or (a = '0' and b = '1' )then
c<= '1';
else
c<= '0';
end if;
end process;
end Behavioral;