beginner_EDA
Full Member level 4
Hi,
I am using Dual Clock fifo from Altera IP Core and instantiating it as:
The input data width(data) is 4 bit at 250 MHz whereas output(q) data width is 8 bit at 100 MHz.
The continuous input stream is controlled by a trigger signal i.e. if trigger_signal == 1, then only write to fifo otherwise not.
I am struggling to understand how wrfull signal can be coordinate with trigger_signal while setting
wrreq <= 1 ?
Similarly how to coordinate rdempty signal with trigger_signal while setting rdreq <= 1 ?
I tried in this way:
but I end up with some stale data on reading side and first 4 bits on writing side.
In VHDL, I think one can do this using FSM with 3 different processes, 1st process for clocked update of Present state, 2nd for State transition and 3rd for output decode.
but in verilog I am facing problem.
Any idea please?
Regards
I am using Dual Clock fifo from Altera IP Core and instantiating it as:
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 rx_dcfifo rx_dcfifo_inst ( .aclr(), .data(payload), .rdclk(test_100_mhz), .rdreq(Rx_fifo_read), .wrclk(test_250_mhz), .wrreq(Rx_fifo_write), .q(Rx_output_from_fifo), .rdempty(Rx_fifo_empty), .rdusedw(r_depth_rx), .wrfull(Rx_fifo_full), .wrusedw(w_depth_rx) );
The input data width(data) is 4 bit at 250 MHz whereas output(q) data width is 8 bit at 100 MHz.
The continuous input stream is controlled by a trigger signal i.e. if trigger_signal == 1, then only write to fifo otherwise not.
I am struggling to understand how wrfull signal can be coordinate with trigger_signal while setting
wrreq <= 1 ?
Similarly how to coordinate rdempty signal with trigger_signal while setting rdreq <= 1 ?
I tried in this way:
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 always @ (posedge test_250_mhz) begin if (trigger == 1) begin Rx_fifo_write <= 1; payload <= ENET0_RX_DATA; end if (trigger == 0) || (Rx_fifo_full == 1) begin Rx_fifo_write <= 0; end end always @ (posedge test_100_mhz) begin if (trigger == 1) begin Rx_fifo_read <= 1; //Rx_output_from_fifo end if (trigger == 0) || (Rx_fifo_empty == 1) begin Rx_fifo_read <= 0; end end
but I end up with some stale data on reading side and first 4 bits on writing side.
In VHDL, I think one can do this using FSM with 3 different processes, 1st process for clocked update of Present state, 2nd for State transition and 3rd for output decode.
but in verilog I am facing problem.
Any idea please?
Regards