DRC Violations. Please Help. Urgent.

[sincplicity]

I am urgently trying to resolve some drc errors for a tsmcN65 process.

The errors are related to enclosure such as DM1.EN.1 with rule defined as:

DM1.EN.1 { @ Enclosure by chip edge >= 2.51 um
DUM1 NOT (SIZE CHIP_CHAMFERED BY -DM1_EN_1)
}

The area is defined by Pr Boundary layer. The defined edge to a violation shows >= 2.5 um distance? What am I missing?

I have requested a DRM but have not received yet. Thanks in advance!

 

[dick_freebird]

Drill into the DRC deck and see what defines "chip edge".
It may not be prBoundary. Might be "bulk" or "scribe" or
something like that.

First step to debugging is understanding what the rule
is supposed to be telling you. Do not assume developer
clarity or communications skills, flowed all the way to the
error report line nor that you're imagining their meaning
as meant.

 

[sincplicity]

Thank you for the fast reply. I pulled up the DRC deck and am looking through it.

Are those key words to look for?

--- Updated May 3, 2024 ---

I found these lines within DRC that are used to define the chip, I believe. ChipWindowUsed is not currently defined.

There is list of EXTENT layers that get mapped to the MT_LAYERS but do not know which extent layer to used. They seem to be defined from physical layers.

#IFDEF ChipWindowUsed
LAYER ChipWindow 500 // layer number for constructing chip boundary
POLYGON xLB yLB xRT yRT ChipWindow
CHIP = PUSH ChipWindow
#ELSE
CHIP = EXTENT MT_LAYERS
//CHIP = EXTENT
//CHIP = EXTENT CELL "*" ORIGINAL
#ENDIF

 

[dick_freebird]

I start with searching the error text, to find the rule code; then follow the logic backwards through the deck until you can identify the layer precursors that make the logical args.

 

[ThisIsNotSam]

looks like metal fill was applied before chip was assembled and violated some rules? hard to say, the screenshot is not informative