doubt in the clock setting in the design of a SAR ADC

[the_falcon]

HI all,
I have a general doubt regarding the implementation of the single ended SAR ADC. I am designing a 10 bit resolution SAR ADC and my sampling rate is 2 KS/s. I use 11 times faster clock than the sampling rate here(22 KS/s) to achieve the conversion cycle.The signal I send at the input of the system is 1 KS/s so that it goes true with the nyquist sampling theorem.

I am using a charge scaling DAC which also carries out the sampling process inherently and hence I dont use a separate sample and hold circuit for sampling.I give this 1KS/s signal in the DAC so that it does the sampling operation at the beginning of each conversion cycle.

I am using a comparator which has two inputs namely reference voltage and the input from the DAC.The reason for me to use reference voltage is that, I use the same reference voltage in the DAC block as well so that it gets added to the signal which is coming out of the DAC to the comparator.

My doubt is that, should I use the same clock rate(22 KS/s) for both the comparator block and also for the SAR logic block which sends the control signals to the DAC block.

If I use the same clock, then I have a situation in the comparator having both the inputs coming at the same rate as the clock rate and so the comparator gets hanged to one level and couldnt do the comparision.

Can anyone of you help me out telling me as where I am going wrong.

falcon

 

[rongo024]

In SAR ADC, clock for both comparator and the controller should be same if you are going to design synchronous SAR. Each clock has positive level and negative level. Generally at positive edge controller plugged the capacitor and positive lever time is used to settle the voltage. for all this time comparator is in reset mode, so any hangup problem might not occur, because at each comparison it gets reset. At the negative edge comparator goes into comparison, from this time to end of the cycle is allowed to compare. At the beginning of next clock the previous value is latched.

If you use linear feedback shift register, then controlling is easy. Anyway you can check some paper from IEEE or search in google to know the clock timing for a conventional SAR.

 

[the_falcon]

Thanks for the reply

I am trying to realise the SAR logic block by verilogA program. But how it is possible for a comparator to compare its both inputs which are changing in the same rate as its own clock. I hope I made my point understandable.Thanks in advance.