doubt about static timing analysis

[sharath666]

If the STA engineer is facing a lot of hold violations, he can tell the PD team to add buffer delays in the data path to solve these...

 

[K-J]

If the STA engineer is facing a lot of hold violations, he can tell the PD team to add buffer delays in the data path to solve these...

If that is what the 'STA engineer' says, then you need to find a different 'STA engineer'. Trying to add buffer delays to fix hold time violations in any FPGA or CPLD design will result in failure.

Kevin Jennings

 

[nitin4u7865]

For Set and hold violation what suggestion we can give to PD team ?

 

[K-J]

For Set and hold violation what suggestion we can give to PD team ?

Setup time violations require one of the following solutions:
- Rewrite the logic to insert registers to break up the combinatorial path into shorter paths
- Slow down the clock
- Switch to a faster part

Hold time violations occur when user generated clocks are created with logic or flip flops. Get rid of those clocks and use a synchronous design approach.

Kevin Jennings

 

[nitin4u7865]

Thanks Kevin,

But is it right option to say "slow down the clock" for set up violation?

Regards,

 

[K-J]

Thanks Kevin,

But is it right option to say "slow down the clock" for set up violation?

Regards,

Slowing down the clock is one of three options that I listed. Choose the option which you feel is 'right' for your design.

 

[D.A.(Tony)Stewart]

Hi all,
Why static timing analysis is not efficient for asynchronous designs..please explain .

Thanks

Asynchronous logic is more efficient in complexity but slower due to ripple propagation time and variance with Vcc and temperature. Thus static timing analysis must include worst case delays, setup, hold times for all nodes. Fastest being cold with Vcc max. And slowest, hot with Vcc min.

So static analysis at nominal conditions is not effective but for quick check, is very efficient.

Async logic is thus more tedious to verify, but efficient in reduction of latches. While Sync logic permits faster clock rates with known fixed delays by design using inverse clock, multiple phases, or same clock edge in terms of latency.

 

[nitin4u7865]

If we have big Soc, how we will go for synthesis and sta?
How we manage constraints at both Top-bottom and Bottom-top approach?

I am quite confused? kindly help me out with..

Thanks in advance